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Ordering number : ENA1345
CMOS IC
LC0710LG
Overview
Monaural CODEC + Audio I/F + Video Driver
The LC07410LG is an IC that integrates a video driver with audio CODEC developed for digital still cameras and other portable equipment. Incorporating 16-bit A/D and D/A converters as well as a microphone amplifier and speaker driver that are necessary for audio recording and playback, the one-chip IC is ideal for use to create audio interfaces.
Functions
Audio Block * Audio interfaces * method 16-bit monaural A/D and D/A converters I2S, Left-justified mode, Right-justified mode * Generates bias voltage (2.3V) for microphone * Supports microphone amplifier * PLL differential inputs (0/+20/+26dB) Input: 12MHz, 13.5MHz, 24MHz, 27MHz * Amplifier with automatic level control (ALC) Sampling frequency: 7.86kHz to 48kHz (-14dB to +34dB) for recording system PLL master mode/slave (EXT) mode * Wind cut HPF * Loopback: ADOUT to DAIN switch incorporated * Two programmable digital filter HSF/Notch filter/LPF/EQ Video Block * Digital volume with * DC direct coupling input/output automatic level control (ALC) for playback system * Built-in 6th order low-pass filter (fc = 7.5MHz) Supports zerocross detection and soft switching * Amplifier gain selectable (6dB or 12dB) * Line output * Drive capacity 75, 1 system On-chip MUTE and POP-noise suppression circuits * Speaker driver Supports VDDS = 5V (piezoelectric speaker supported) BTL drive, rated output of 350mW at 8, VDDS = 3V 1W at 8, VDDS = 5V Idling current adjustable Supports BEEP input, volume level switchable
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Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
D0308 MS 20081010-S00002 No.A1345-1/36
LA07410LG
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REG Block * 3.0V output linear regulator for Audio Block * Overcurrent protective function (typ: 200mA) * Quick discharge activity * 3-line serial register control * Digital I/O 1.8V supported
* Supply voltage VDDIO = 1.8V/3.3V (1.71 to 3.6V) VDDA = VDDP =3 .0V (2.7 to 3.6V) VDDR = 3.3V (3.2 to 3.6V) VDDV = DVDD = 3.3V (2.7 to 3.6V) VDDS = 3.3/5V (2.7 to 5.5V) * Operating ambient temperature: -20 to +80C
Function comparison table of LC07410 and LC074146
Function Logic I/O 1.8V accepted 3V Regulator BEEP sound generator PLL frequencies EXT-BEEP GAIN ALC attack speed ALC recovery speed ALC noise gate function Digital filters Wind cut HPF +2 programmable filters Wind cut HPF + EQ (HSF) + Notch flexible 0dB, -15/-18/-21dB 2step variable 3step variable Pre-fix -12/-15/-18/-21dB monotonic monotonic LC07410 LC074146
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage (5V system) Maximum supply voltage (3V system) Input voltage Output voltage Input/output voltage Allowable operating voltage range VIN max VOUT max VIO max VDDSRANGE VDDRRANGE VDDARANGE VDDIORANGE Allowable power dissipation Operating ambient temperature Storage ambient temperature Pd max Topr Tstg VDDS VDDR VDDA, VDDP, VDDV, DVDD VDDIO Ta = 80C * -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 2.7 to 5.5 3.2 to 3.6 2.7 to 3.6 1.71 to 3.6 500 -20 to +80 -55 to +125 V V V V V V V mW C C VDD3 max Other than VDDS -0.3 to 4.0 V Symbol VDD5 max VDDS Conditions Ratings -0.3 to 7.0 unit V
* Mounted on a specified board: 40mmx50mmx0.8mm, glass epoxy board 2S2P (4-layer board)
No.A1345-2/36
LA07410LG
Recommended Operating Range at Ta = 25C, VSSV = DVSS = VSSR = VSSA = 0V
Parameter Supply voltage Symbol VDDIO DVDD VDDana VDDV VDDR VDDS Supply voltage gap VDDDV VDDDR VDDID VDDPR VDDPA VDDAS VDDVS Inpupt high level voltage Input low level voltage Input clock frequency Input clock duty VIH VIL fMCLK DutyMCLK VDDIO pin DVDD pin VDDP, VDDA pin VDDV pin VDDR VDDS pin DVDD-VDDV DVDD-VDDR VDDIO-DVDD VDDP-VDDR VDDP-VDDA VDDA-VDDS VDDV-VDDS (*1) (*1) MCLKIN pin MCLKIN pin 0.8xVDDIO DVSS 2.012 0.45 0.50 Conditions min 1.71 2.7 2.7 2.7 3.2 2.7 Ratings typ 3.3 3.3 3.0 3.3 3.3 3.3/5.0 max 3.6 3.6 3.6 3.6 3.6 5.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 VDDIO 0.2xVDDIO 27 0.55 V V V V V V V V V V V V V V V MHz % unit
(*1) Applicable pins: PDNB, CSB, SCK, SDA, TESTIN, DAIN, MCLKIN, BCLK, LRLK (in input mode)
Electrical Characteristics at Ta = 252C, VDDIO = 1.71 to 3.6V, VDDA = VDDP = VDDV = DVDD = 2.7 to 3.6V, VDDR = 3.2 to 3.6V, VSSS = 2.7 to 5.5V, VSSV = DVSS = VSSR = VSSA = 0V
Parameter Input high level current Inputp low level current Output high level voltage Output low level voltage Symbol IIH IIL VOH1 VOL1 VI = VDDIO (*1) VI = DVSS (*1) IOH = -1mA (*2) IOL = 1mA (*2) -1 0.8xVDDIO 0.2xVDDIO Conditions min Ratings typ max +1 A A V V unit
(*1) Applicable pins: PDNB, CSB, SCK, SDA, TESTIN, DAIN, MCLKIN, BCLK, LRCK (in input mode) (*2) Applicable pins: ADOUT, BCLK, LRCK (in output mode)
Analog Characteristics at Ta = 25C, VDDA = VDDP = 3.0V, VDDIO = DVDD = VDDS = VDDV = VDDR = 3.3V, fs=48kHz
Parameter Current drain REC time PB (LINE) time PB (SPK) time Video block 1 Video block 2 Power down time current MIC MIC amplifier gain VGmic VIN = -30dBV, 1kHz, MGAIN[1:0] = 01 VIN = -30dBV, 1kHz, MGAIN[1:0] = 10 VIN = -30dBV, 1kHz, MGAIN[1:0] = 11 MIC amplifier output THD+N MIC amplifier output noise voltage MIC bias output voltage Vmicpwr RL = 5k 2.2 2.3 2.4 V VNOmic MIC IN no signal, A-weighted, MGAIN[1:0] = 11 -88 -82 dBV THDNmic VIN = -30dBV, 1kHz, MGAIN[1:0] = 11 -1 19 25 0 20 26 -80 1 21 27 -70 dB dB dB IDDRA1 IDDPA2 IDDPA3 IDDV1 IDDV2 IDDPD REG/PLL/MIC/PGA/ADC on, no input signal REG/PLL/DAC/LINE on, no input signal REG/PLL/DAC/SPK on, no input signal VDDV, no input signal VDDV, Video in = white 50% VDDA+VDDP+VDDR+VDDS+VDDV+DVDD+VDDIO, clock stopped 9.0 8.0 11.0 4.0 8.0 13.8 12.2 15.2 6.1 12.8 1.0 18.0 16.0 21.0 8.0 16.0 10 mA mA mA mA mA A Symbol Conditions min Ratings typ max unit
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No.A1345-3/36
LA07410LG
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Parameter ALC Gain change Gain control range DGalc VGalc -14 1 +34 dB dB Symbol Conditions min Ratings typ max unit
ADC: ALCIN input, ALCOFF, PGA Gain = 0dB Analog input voltage THD+N Dynamic range S/N ratio DAC Digital volume change DGvol1 DGvol2 DGvol3 LINE: DACLINE Gain = 0dB, DVOL = 0dB Analog output voltage THD+N Dynamic range S/N ratio SPK SPK amplifier gain SPK output distortion SPK output noise voltage SPK maximum rated output BEEP gain VGbp BTL, RL=8 BPVOL[1:0] = 00 BTL, RL = 8 BPVOL[1:0] = 01 BTL, RL = 8 BPVOL[1:0] = 10 BTL, RL = 8 BPVOL[1:0] = 11 Regulator Regulator output voltage Video driver Video amplifier gain VGvideo VGAIN[1:0] = 00, VDIN = 1Vp-p 100% white VGAIN[1:0] = 10, VDIN = 0.5Vp-p 100% white Frequency characteristics Fva f = 8MHz/100kHz f = 20MHz/100kHz Input impedance Rvin 100 5 11 6 12 -4.5 -40 120 7 13 0 -35 dB dB dB dB k VOreg IOUT = 20mA 2.9 3.0 3.1 V -2 -16 -19 -22 0 -15 -18 -21 2 -14 -17 -20 dB dB dB dB VGsp HDsp VNOsp VOMsp SPKIN = -9dBV, 1kHz , BTL, RL = 8 SPKIN = -9dBV, 1kHz SPKIN no signal, RL = 8 RL = 8, THD = 3% 300 11 12 0.2 -86 350 13 1 -80 dB % dBV mW Voutda THDNda DRda SNda 0dBFS, 1kHz 0dBFS, 1kHz -60dBFS, A-weighted A-weighted 80 80 0.6xVDDA -83 88 88 -74 Vp-p dB dB dB +12dB to -10dB -11dB to -42dB -44dB to -64dB 0.5 1 2 dB dB dB Vinad THDNad DRad SNad 0dBFS, 1kHz -1dBFS, 1kHz -60dBFS, A-weighted ALCIN no signal, A-weighted 80 80 0.6xVDDA -80 86 86 -74 Vp-p dB dB dB
ADC Filter Characteristics
Parameter Resolution Passband Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB 0 to 20kHz -69 58 0.0000385fs 0.045dB 0 0.5465fs 0.045 dB dB 1/fs Hz 1.85Hz@fs = 48kHz Conditions min Ratings typ 16 0.4535fs max Bit 21.8kHz@fs = 48kHz 26.2kHz@fs = 48kHz unit Remarks
No.A1345-4/36
LA07410LG
DAC Filter Characteristics
Parameter Resolution Passband Stopband Passband ripple Stopband attenuation Output data delay HPF cutoff frequency -3dB -63 48 0.0000385fs 0.015dB 0 0.5465fs 0.015 dB dB 1/fs Hz 1.85Hz@fs = 48kHz Conditions min Ratings typ 16 0.4535fs max Bit 21.8kHz@fs = 48kHz 26.2kHz@fs = 48kHz unit Remarks
Switching Characteristics
Parameter PLL CKIN frequency fCKI PLL used EXT input present BCLK frequency fBCK FBCLK = 0 FBCLK = 1 BCLK duty cycle LRCK frequency LRCK duty cycle CLK transition time CLK transition time dtBK fLR dtLR trCK tfCK Rise time, MCLKIN/BCLK/LRCK inputs present Fall time, MCLKIN/BCLK/LRCK inputs present 45 7.86 45 50 12 2.012 64fs 32fs 50 55 48 55 10 10 % kHz % ns ns 27 24.576 MHz MHz Symbol Conditions min Ratings typ max unit
Package Dimensions
unit : mm (typ) 3370
TOP VIEW 3.6 BOTTOM VIEW 0.55
6 78 4.4 0.45 1 2 34 5 0.5
FE 0.3
0.0 NOM
D CB A 0.5
SIDE VIEW
0.85 MAX
SANYO : FLGA40(4.4X3.6)
No.A1345-5/36
LA07410LG
Pin Assignment
NC ADOUT VDDIO DVSS SCK NC
8
MCLKIN LRCK DVDD TESTIN SDA CSB
7
MCLKO VDDR BCLK DAIN PDNB VDREF
6
VSSR REGOUT VSSV VDOUT
5
VCOFIL VDDP
Top view
VDDV VDIN
4
ALCIN MICPWR VDDA BEEP VSSS SPOUTP
3
MICOUT MICINN VSSA LOUT2 VDDS SPOUTN
2
NC MICINP VREF LOUT1 SPKIN NC
1 A B C D E F
Block Diagram
3.0V 3.3V
MICOUT
VCOFIL
VREG
VDDP
VSSR
ALCIN
MICPWR
MIC Power MIC AMP
LDO
PLL
-14 to +34dB
MCLKIN MCLKO
MICINP MICINN
ADC
Digital filter
0/+20/+26dB VDDA VSSA VREF
ADOUT DAIN
VREF
0/4/6/8dB
ALC CTL MUTE
0/6dB
I/F
VDDIO
VDDR
BCLK LRCK
1.8V or P/ 3.3V DSP 3.3V
LINE OUT
LOUT1
DAC
VOL
DVDD DVSS TESTIN
LOUT2
BEEP GEN
SPKIN BEEP +6/+12dB
SDA
SPK AMP
SPOUTN SPOUTP VSSS VDIN
LPF
VDOUT VDDV
REF
VDREF VSSV
MODE CTL
PDNB
SCK CSB
VDDS
1.8V or 3.3V
3.3V or Li+ batt.
3.3V
Video out
VIDEO DAC
No.A1345-6/36
LA07410LG
Pin Function
Pin No. B3 Pin name MICPWR I/O O
(Note) I/O: I => input, Is => Schmitt input, O => output, IO s=> Schmitt input/output
Function Microphone power supply output (2.3V) Equivalent circuit
B1
MICINP
I
Microphone amplifier input (+ side)
70k
B2
MICINN
I
Microphone amplifier input (- side)
70k
C3 C1
VDDA VREF
- O
Analog block power supply (3V) 3V analog power supply reference voltage output
C2 D1
VSSA LOUT1
- O
Analog block ground (0V) Line output 1
D2
LOUT2
O
Line output 2
D3
BEEP
I
BEEP signal input, mixed to speaker amplifier
5k 5k 107k
D3
E1
SPKIN
I
Speaker amplifier input
10k
E1
5k
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No.A1345-7/36
LA07410LG
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Pin No. E2 F2 Pin name VDDS SPOUTN I/O - O Function Speaker analog power supply Speaker output (-) Equivalent circuit
F3
SPOUTP
O
Speaker output (+)
E3 E4 F4
VSSS VDDV VDIN
- - I
Speaker analog ground Video driver analog power supply Video signal input
120k
120k
F5
VDOUT
O
Video signal output
F6
VDREF
O
Video VREF
500 500
50k
E5 E6 F7 E8 E7 D8 C7 C8 D7
VSSV PDNB CSB SCK SDA DVSS DVDD VDDIO TESTIN
- Is Is Is Is - - - I
Video driver ground Reset (negative polarity) Chip select (negative polarity) Microcontroller IF Serial clock Serial data input Digital ground (0V) Digital power supply (3.3V) Digital I/O power supply (3.3V/1.8V) Test input (VSS fixed in normal operation) Microcontroller IF Microcontroller IF
schmitt
D6
DAIN
I
DAC serial data input
B8
ADOUT
O
ADC serial data output
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No.A1345-8/36
LA07410LG
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Pin No. B7 Pin name LRCK I/O IOs LR clock input Function Equivalent circuit
schmitt
C6
BCLK
IOs
Bit clock input
A6
MCLKO
O
Master clock output (Default: Set to Low, serial setting enables output/Addr: 16h)
A7
MCLKIN
I
Master clock input
B6 B5
VDDR REGOUT
- O
Regulator power supply input (3.3V) Regulator output pin
144k 100k 100
A5 A4
VSSR VCOFIL
- O
Regulator block ground VCO filter pin
100
B4 A3
VDDP ALCIN
- I
PLL block supply (3.0V) ALC amplifier input
20k
A2
MICOUT
O
Microphone amplifier output
No.A1345-9/36
LA07410LG
Interface Timing Characteristics
Parameter Microcontroller serial interface timing SCLK cycle time SCLK high period SCLK low period Data setup time Data hold time CSX rise to SCLK wait time SCLK to CSX rise wait time Rise time Fall time Audio data timing Clock phase (Note 2) Clock phase (Note 3) Data delay time Data setup time Data hold time tPH tPH tDD tSUA tHDA 0 1T 1T 75 1/(128fs) 75 ns ns ns ns ns tCYC tSH tSL tSU tHD tWSCLK tWCSX tSR tSF 4T 2T 2T 2T 2T 0T 4T 8T 4T 4T 4T 4T 2T 6T 50 50 ns ns ns ns ns ns ns ns ns Symbol Ratings min typ max unit
Note 1: T = 1/fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK = 10MHz, T = 100ns, 2T = 200ns Note 2: LRCK and BCLK are inputs in Slave mode. The MCLK timing needs only to be synchronized with LRCK and BCLK and its phase is irrelevant. Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency. Note 4: The load of output pin: 30pF.
Microcontroller Serial Interface Timing Diagram
CSB tCYC tWSCLK tSH tSL tWCSX
SCK tSU tHD SDA A[7] tSF tSR Dn[0]
Audio Data Timing Diagram
LRCK tPH BCLK tDD ADOUT tSU DAIN tHD tPH
No.A1345-10/36
LA07410LG
Audio Data Formats * I2S mode
LRCK BCLK ADOUT 15 14 1 Lch Data 0 15 14 1 Rch Data 0
* Left-justified mode
LRCK BCLK ADOUT 15 14 1 0 15 14 1 0 15
Lch Data
Rch Data
* Right-justified mode
LRCK BCLK ADOUT 0 15 14 Lch Data 1 0 15 14 Rch Data 1 0
PLL/BCLK/LRCK Master/Slave
Pin No. A7 A6 Pin Name MCLKIN MCLKO Slave Mode (PLL: OFF) Input Output (through) Master Mode (PLL: ON) Input Output (PLL = 256fs)
Pin No. B7 C6
Pin Name LRCK BCLK
Slave Mode (ADF_MASTER = 0) Input Input
Master Mode (ADF_MASTER = 1) Output Output
No.A1345-11/36
LA07410LG
Microcontroller Serial Interface
The internal registers values are written by the serial interface consisting of the three CSB, SCK, and SDA lines. When the CSB pin is set low, the LC07410LG is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (39h) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00h. Transferring data to one address
A[7:0] D[7:0] X
CSB SCK SDA X X
A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] ADDRESS BYTE WRITE DATA (address A)
: Designated address : Register data : Invalid
X X
Transferring data to contiguous addresses
CSB SCK SDA X X
A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] ADDRESS BYTE WRITE DATA (address A) WRITE DATA (address A+1) Dn[0]
X X
No.A1345-12/36
LA07410LG
Specification Details
* Power down/system reset When the PDNB pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for each block. A 0 on the PDNB pin also triggers a system reset. After the power is first applied, the system must be reset without fail. [See the section on "Checkpoint_2) Resetting"] After resetting, the contents of the serial port register are initialized. The VREF buffer is activated by releasing power down mode by setting the PDNB pin from 0 to 1, and then by setting VREF_BIAS[1:0] to 01. When VREF_BIAS [1:0] is set to 10, VREF starts. Along with the start of VREF, the LINE output pin is biased to 1/2VDDA. Once the VREF voltage has stabilized, VREF_BIAS [1:0] must be set to 11 (normal state). Reference voltage generator circuit VREF_BIAS: Voltage Reference Bias
ADRS 01h Bit [5:4] Name VREF_BIAS Init 00b Sets the reference voltage circuit (VREF pin). 11: Normal operation (standard resistor value) 10: Quick rise to reference voltage <*1> 01: Activates IREF bias, VREF OFF 00: Power down <*1> The target voltage is reached quickly by connecting a low-resistance element in the "reference voltage generation circuit." During normal operation, a standard resistance is recommended in order to save power.
* Bold letters indicate initial settings.
Description
Power Control
ADRS 00h Bit [7] Name MIC_PDX Init 0b MIC amplifier circuit, power control 1: power on [6] MIC_PWR_PDX 0b 0: power down Description
MIC power circuit (MIC_PWR pin), power control 1: power on 0: power down
[5]
PGA_PDX
0b
PGA circuit, power control 1: power on 0: power down
[4]
ADC_PDX
0b
ADC circuit, power control 1: power on 0: power down
[3]
DAC_PDX
0b
DAC circuit, power control 1: power on 0: power down
[2]
SEL_PDX
0b
Selector (LOUT2) circuit, power control 1: power on 0: power down Line out circuit (LOUT1) circuit, power control 1: power on 0: power down Speaker amplifier circuit, power control 1: power on 0: power down
[1]
LO_PDX
0b
[0]
SP_PDX
0b
01h
[2]
PLL_PDX
0b
PLL circuit, power control 1: power on 0: power down (PLL-EXT mode)
[1]
REG_PDX
0b
Regulator circuit, power control 1: power on 0: power down
[0]
VD_PDX
0b
Video driver circuit, power control 1: power on 0: power down
Sampling Frequency Setting Set sampling frequency used by FS [4:0] register. This is necessary to make it for correctly setting digital frequency characteristic and ALC damping time constant. The setting is adjusted to a value that is the closest to fs used.
ADRS 15h Bit [3:0] Name FS Init 1000b Sampling Frequency Setting 1000: 48kHz/0111: 44.1kHz/0110: 32kHz/0101: 24kHz 0100: 22.05kHz/0011: 16kHz/0010: 12kHz/0001: 11.025kHz 0000: 8kHz Note: This setting doesn't synchronize with PLL setting. It is necessary to set it individually respectively. Refer to the page of PLL function explanation for PLL setting. Description
No.A1345-13/36
LA07410LG
* 3V Regulator Built-in 3V Regulator for VDDA,VDDP. The regulator starts by setting as REG_PDX = 1. Output current is 100mA (typ). It provides with max 200mA (typ) output current limiter for over-current protective function. * Microphone (MIC) amplifier The microphone amplifier has a differential input and a gain of +26dB (typ). Its gain can also be set to +20dB or 0dB by register MGAIN [1:0]. Its input resistance is 70k (typ). The MICPWR is a power output pin for the microphone, and its output voltage is 2.3V (typ 0.767xVDDA). The maximum output current is 20mA. The microphone amplifier is placed in the power down mode by setting MIC_PDX to 0. When MIC_PWR_PDX is set to 0, the microphone power supply circuit is placed in the power down mode.
ADRS 02h Bit [5:4] Name MIC_GAIN Init 01b MIC amplifier circuit, gain setting 11: 26dB 10: 20dB 01: 0dB 00: 0dB Description
* Recording system automatic level control (ALC) The amplifier gain of the PGA (Programmable Gain Amplifier) must be automatically adjusted so that the A/D converter output audio level is setup to the predetermined value. The gain can be varied within a range (maximum) of -14dB to +34dB. When using ALC in the recording system, set REC_ALC to 1 and PB_ALC to 0 (recording system ALC mode). When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the PGA is placed in the manual mode, and the amplifier gain is fixed to the value of the ALC_GAIN register setting. When PGA_PDX is set to 0, the PGA is placed in the power down mode. During normal use, the state of PGA_PDX must be switched at the same time as ADC_PDX. For further details on operation, refer to "Description of ALC/limiter (Automatic Level Control) operation." Any of eight recording ALC levels (in 1dB steps from -3dBFS to -10dBFS) can be set using the ALC_VAL register.
ADRS 03h Bit [6:4] Name ALC_VAL Init 001b Set the ALC limiter level 000: -3dBFS 001: -4dBFS 010: -5dBFS 011: -6dBFS 100: -7dBFS 101: -8dBFS 110: -9dBFS 111: -10dBFS [2:0] 04h [6:4] [2:0] 05h [6:4] [2:0] 06h [6:4] [2:0] 07h 08h [2:0] [7] ALC_FA1 ALC_THA ALC_FA2 ALC_THR1 ALC_FR1 ALC_THR2 ALC_FR2 ALC_FR3 ALC_FULLEN 010b 010b 100b 011b 100b 011b 100b 100b 0b Attack coefficient 1 setting Set the attack speed switch over thresh Attack coefficient 2 setting Set the recovery speed switch over thresh1 Recovery coefficient 1 setting Set the recovery speed switch over thresh2 Recovery coefficient 2 setting Recovery coefficient 3 setting Sets the full scale detection mode 1: Performs attack operation regardless of the ALCZCD setting when a full scale is detected. 0: Normal operation [6] ALC_ZCD 1b Controls the gain change operation at zerocross timing. 1: Changes the gain at zerocross timing. 0: Changes the gain without waiting for a zerocross timing. [5:4] ALC_ZCDTM 01b Set the zerocross detection timeout time. Valid when [ALC_ZCD] = 1. 11: 2048/fs 10: 1024/fs 01: 512/fs 00: 256/fs * It becomes the above-mentioned 1/4 times at fs 8k to12kHz, It becomes the above-mentioned 1/2 times at fs 16k to 24kHz. [3:2] ALC_TLIM 01b Set the inter-zerocross attack limit. 11: 4dB 10: 2dB 01: 1dB 00: 0.5dB Valid when [ALC_ZCD] = 1 [1:0] ALC_RWT 10b Set the recovery alert time 11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs * It becomes the above-mentioned 1/4 times at fs 8k to 12kHz, It becomes the above-mentioned 1/2 times at fs 16k to 24kHz. Description
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ADRS 09h Bit [7] Name ALC_NGEN Init 0b Set the noise gate function 1: Valid 0: Invalid [6:4] [3:2] [1:0] 0Bh [5:0] ALC_NGTH ALC_NGDT ALC_NGRT ALC_VMAX 100b 10b 01b 0Eh Set the noise gate silent detection thresh level Set the noise gate silent detection time/See the gain attenuation time Set the noise gate reset time Set the maximum PGA gain value (Init value = 0Eh: 0dB) Refer to "ALC Circuit Gain Setting Table." 0Ch [5:0] ALC_GAIN 0Eh Set the manual mode PGA gain value (Init value = 0Eh: 0dB) Refer to "ALC Circuit Gain Setting Table." 0Dh [1:0] REC_ALC PB_ALC 10b ALC mode setting 10: REC ALC, PB manual gain setting 01: PB ALC, REC manual gain setting 00/11: ALC OFF, REC/PB manual gain setting See the section on "Description of ALC Operation." Description
* Attack coefficient 1
FA1[2:0] 000 001 010 011 100 101 110 111 1dB Attenuation time* 1/fs 2/fs 4/fs 8/fs 16/fs 32/fs 64/fs 128/fs fs = 48kHz 24kHz 12kHz 20.83s 41.67s 83.33s 166.7s 333.3s 666.6s 1.333ms 2.666ms
* Attack coefficient 2
FA2[2:0] 000 001 010 011 100 101 110 111 1dB Attenuation time* 1/fs 2/fs 4/fs 8/fs 2 /fs 210/fs 211/fs 2 /fs
12 9
fs = 48kHz 24kHz 12kHz 20.83s 41.67s 83.33s 166.7s 10.66ms 21.33ms 42.67ms 85.33ms
* At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed).
* Attack speed switch over thresh level
THA[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL +1dB +2dB +3dB +4dB +5dB +6dB +7dB +8dB
* Recovery coefficient 1
FR1[2:0] 000 001 010 011 100 101 110 111 FS/s* 13.2 6.6 3.3 1.65 0.828 0.424 0.212 0.106
* Recovery coefficient 2
FR2[2:0] 000 001 010 011 100 101 110 111 FS/s* 3.3 1.65 0.828 0.424 0.212 0.106 0.053 0.026
* Recovery coefficient 3
FR3[2:0] 000 001 010 011 100 101 110 111 FS/s* 0.828 0.424 0.212 0.106 0.053 0.026 0.013 0.006
* Value at fs = 48kHz, 24kHz, 12kHz
No.A1345-15/36
LA07410LG
* Recovery speed switch over thresh level 1
THR1[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL -26dB -24dB -22dB -20dB -18dB -16dB -14dB Prohibition
* Recovery speed switch over thresh level 2
THR2[2:0] 000 001 010 011 100 101 110 111 Level to ALC_VAL -20dB -18dB -16dB -14dB -12dB -10dB -8dB Prohibition
* Zerocross timeout period
ZCDTM[1:0] 00 01 10 11 Timeout period* 1024/fs 2048/fs 4096/fs 8192/fs fs = 48k/24k/12kHz 21.33ms 42.67ms 85.33ms 170.7ms
* Recovery alert time
RWT[1:0] 00 01 10 11 Standby time 128/fs 256/fs 512/fs 1024/fs fs = 48k/24k/12kHz 2.67ms 5.33ms 10.67ms 21.33ms
* At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed).
ALC Circuit Gain Setting Table ALC_VMAX[5:0]/ALC_GAIN[5:0]
[5:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h GAIN -14dB -13dB -12dB -11dB -10dB -9dB -8dB -7dB -6dB -5dB [5:0] 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h GAIN -4dB -3dB -2dB -1dB 0dB 1dB 2dB 3dB 4dB 5dB [5:0] 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh GAIN 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB [5:0] 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h GAIN 16dB 17dB 18dB 19dB 20dB 21dB 22dB 23dB 24dB 25dB [5:0] 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h GAIN 26dB 27dB 28dB 29dB 30dB 31dB 32dB 33dB 34dB
* Noise gate silent detection thresh
NGTH[2:0] 000 001 010 011 100 101 110 111 Thresh -35dBFS -41dBFS -47dBFS -53dBFS -59dBFS -65dBFS -71dBFS -77dBFS
* Noise gate silent detection time/Gain attenuation speed (0dB -35dB)
fs = 48kHz NGDT[1:0] 00 01 10 11 Detection time* 213/fs 2 /fs 215/fs 216/fs
14
fs = 48kHz Gain attenuation time* 30x210/fs 30x2 /fs 30x212/fs 30x213/fs
11
24kHz 12kHz 0.17s 0.34s 0.68s 1.36s
24kHz 12kHz 0.64s 1.28s 2.56s 5.12s
* At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz
* Noise gate reset time (-35dB 0dB)
fs = 48kHz NGRT[1:0] 00 01 10 11 Gain reset time* 30x28/fs 30x2 /fs 30x210/fs 30x211/fs
9
24kHz 12kHz 0.16s 0.32s 0.64s 1.28s
* At fs = 32k to 48kHz setting. 1/4 times at 8k to 12kHz, 1/2 times at 16k to 24kHz (48kHz, 24kHz, 12kHz become the same speed).
No.A1345-16/36
LA07410LG
Relation Between Output level and Recovery Speed (FR,THR)
FR1 FR2 FR3 ALC VAL THR2 THR1 Signal after ADC
FR value is shown by inclination (FS/s) of the shape of recovery waves. (FS = Full Scale = 0dBFS) Description of ALC/Limiter (automatic level control) operation Note: Whatever is contained inside the parentheses " " is applicable in the PB-ALC mode. The amplifier gain "digital volume value" of the PGA (programmable gain amplifier) is automatically adjusted so that the A/D converter output audio level "digital volume output" is set to the ALC value "ALC_VAL [2:0]". The PGA "digital volume" gain can be varied in the -14dB to +34dB range. The maximum value "ALC_VMAX [5:0]" can be set in this variable range. * ALC settings * Power-saving function When [PGA_PDX] is 0, the ALC circuit and PGA circuit are set to power down mode. * Manual function (ALC OFF) At REC_ALC = PB_ALC = 0, it become manual mode. PGA gain is fixed by value of ALC_GAIN [5:0] Digital volume value is fixed by EVR_GAIN [6:0] * System operation ALC is performed by feeding back the A/D converter "digital volume" data. Accordingly, configure the settings as shown in the table below in order for the ALC functions to be activated.
Resister REC-ALC PGA_PDX ADC_PDX DAC_PDX REC_ALC PB_ALC 1 1 x 1 0 Mode PB-ALC 0 x 1 0 1
(1) Attack operations When the ADC "digital volume" output exceeds the ALC limiter level, ALC_VAL[2:0], the PGA gain "digital volume value" is lowered. When the rate of gain attenuation is ALC_THA[2:0] or more, ALC_FA1[1:0] results, but when the value is less than ALC_THA[2:0], ALC_FA2[1:0] results. When zero-cross detection ALC_ZCD is set to 1, the gain attenuation from zero-cross to zero-cross is limited by the limit value ALC_TLIM[1:0].
No.A1345-17/36
LA07410LG
(2) Recovery operations When the ADC "digital volume" output is less than 2dB of the ALC limiter level, ALC_VAL[1:0], and this status continues for the recovery wait time, ALC_RWT[1:0], the PGA gain "digital volume value" is increased. The rate of gain increase is performed using the recovery coefficients given below according to the amplitude. Recovery coefficients by level
Output level FR The increase in PGA gain "digital volume value" is carried out continuously while the ADC "digital volume" remains less than 2dB of ALC_VAL[1:0]. The amount of increase in zero-cross to zero-cross PGA gain "digital volume value" is at most 1dB. Functions common to (1) and (2) * Zero cross detection When [ALC_ZCD] is set to 0, the PGA gain "digital volume value" changes regardless of the zero cross timing of the A/D converter "digital volume" output. When [ALC_ZCD] is set to 1, the PGA gain "digital volume value" changes at the zero cross timing of the A/D converter "digital volume" output. * Zero cross timeout Even if the PGA "digital volume" output does not cross zero, as long as there is no zero cross signal during the zero-cross timeout value, ALC_ZCDTM[1:0], a zero-cross signal is generated internally and the PGA gain "digital volume value" is changed. ALC Wave Forms
Input
Gain
ALC_VAL
Output
ALC_VAL -2dB
b a
c
e d
f
g
h
a: Attack (FA1) b: Attack (FA2) d: Recovery wait time (RWT) e: Recovery (FR1) f: Recovery (FR2) g: Recovery (FR3) c, h: Stable
No.A1345-18/36
LA07410LG
* Noise gate function The noise gate function is enabled when NGEN is 1. This function cannot be used during PB-ALC mode. If the PGA input level continues at or below NGTH[2:0] for the period NGDT[1:0], the volume after ADC output is decreased from 0dB to approximately -35dB at the rate NGDT[1:0]. If the PGA input level rises to NGTH+6dB or more, the volume after ADC output is increased from approximately -35dB to 0dB at the rate NGRT[1:0].
Silent detection thresh Input
Noise gate: Valid
Output
Noise gate: Invalid
Output
Amplitude detection phase
Silent detection thresh
Return level of detection thresh
VOL gain
Silent detection time
* ADC PGA output undergoes AD conversion and is output as 16-bit serial audio data. The three formats, I2S, left justified, and right justified are supported. If ADC_PDX is set to 0, the ADC block is powered down. An interval of 64/fs is used as the ADC initialization interval (initialization + data delay) from the point power down is canceled. When power is turned on, initialization is required when switching the system clock. A digital HPF for canceling DC offset is built-in. The cut-off frequency, fc, is 1.85Hz (@fs = 48kHz). The full-scale voltage (0dBFS) is 0.6xVDDA. * DAC 16-bit serial audio data undergoes DA conversion. The three formats, I2S, left justified, and right justified are supported. If DAC_PDX is set to 0, the DAC block is powered down. An interval of 58/fs is used as the DAC initialization interval (initialization + data delay) from the point power down is canceled. When power is turned on, initialization is required when switching the system clock. The full-scale voltage (0dBFS) is 0.6xVDDA.
No.A1345-19/36
LA07410LG
Audio Data Formats
ADRS 0Dh Bit [3] Name AD_MUTE Init 0b Sets the ADC output MUTE 1: Enables MUTE function 0: Disables MUTE function [2] FBCLK 0b Sets the BCLK frequency 1: 32fs 0: 64fs 0Eh [4] ADF_MASTER 0b ADF circuit 1: Master mode, BCLK and LRCLK pins are set for output. 0: Slave mode, BCLK and LRCLK pins are set for input. [3] ADF_DAC_INV 0b Sets the DAC input data of the ADF circuit. 1: Inverted 0: Non-inverted [2] ADF_ADC_INV 0b Sets the ADC input data of the ADF circuit. 1: Inverted 0: Non-inverted [1:0] ADF_MODE 00b Define the data format of the ADF circuit. 11, 10: Right justification (right-justified) 01: Left justification (left-justified) 00: I2S See the section on "Audio Data Formats." Description
* Loopback (a) Loopback mode (ADF_LB = 1) Internal connect between ADOUT and DAIN, This enables the MIC input to be output to the line or speaker without recording or playback operation. In this case, external output through ADOUT is enabled but external input through DAIN is disabled. (b) Standard mode (ADF_LB = 0) The DAIN external input is enabled and the internal switch for ADOUT and DAIN is released.
ADOUT I/F DAIN
ADRS 0Fh
Bit [5]
Name ADF_LB
Init 0b Loopback setting 1: ADCInternal loopback in DAC is done
Description
0: ADCInternal loopback in DAC is not done
Programmable Digital Filter
ADC DAIN ADOUT DAC
Programmable Filter 1
Windcut HPF
Programmable Filter 2
* Windcut HPF (1st order) WIND_CUT [5:4] turns off the high-pass filter (through) when initialized to (00). Regardless of the sampling frequency (fs), the cutoff frequency (fc) is 400Hz when WIND_CUT [5:4] is set at 11, 300Hz at 10, 200Hz at 01 and OFF at 00.
ADRS 0Dh Bit [5:4] Name WIND_CUT Init 00b WIND_CUT Function (HPF fc setting) 11: 400Hz 10: 300Hz 01: 200Hz 00: OFF Description
No.A1345-20/36
LA07410LG
* Programmable Filter A second order biquad filter that allows coefficients to be freely set is used for the programmable filter. A notch filter, LPF, or other filter can be configured by setting the coefficients, a1, a2, b0, b1, and b2, in 16-bit 2's complement notation in a register. Make sure that the corresponding filter is OFF when setting or modifying coefficients.
ADRS 0Dh Bit [7] Name FILTER2 Init 0b Set the programmable filter2 1: ON 0: OFF [6] FILTER1 0b Set the programmable filter1 1: ON 0: OFF 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] A1[15:8] A1[7:0] A2[15:8] A2[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0] A1[15:8] A1[7:0] A2[15:8] A2[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0] 00h 00h 00h 00h 40h 00h 00h 00h 00h 00h 00h 00h 00h 00h 40h 00h 00h 00h 00h 00h Set the programmable filter2 coefficient b2 Set the programmable filter2 coefficient b1 Set the programmable filter2 coefficient b0 Set the programmable filter2 coefficient a2 Set the programmable filter2 coefficient a1 Set the programmable filter1 coefficient b2 Set the programmable filter1 coefficient b1 Set the programmable filter1 coefficient b0 Set the programmable filter1 coefficient a2 Set the programmable filter1 coefficient a1 Description
* DSP Route Setting The route of digital filter is selected by the SEL_USE_DSP register.
ADRS 0Fh Bit [1] Name SEL_USE_DSP Init 0b DSP Route setting 1: DSP inserted in PB (DAC) side 0: DSP inserted in REC (ADC) side Note: Programmable Filter and Wind Cut HPF functions serve as the DSP functions. Description
No.A1345-21/36
LA07410LG
* Digital Volume Contained inside the D/A converter is a digital volume control, and by setting EVR_GAIN [6:0], the gain level can be attenuated from +12dB (max) to -64dB or muted. When EVR_ZCD is 0, the gain is changed immediately after setting EVR_GAIN [6:0]. When EVR_ZCD is 1, after setting EVR_GAIN [6:0] the gain is changed at the zero cross timing of the audio signals. The timeout time for zero cross detection can be set using EVR_ZCDTM [1:0]. When EVR_SOFTSW is 1, the soft switching operation is performed, and after the EVR_GAIN [6:0] setting has been changed, the gain automatically changes in 1-step increments until it arrives at the predetermined value. The period of gain change can be set using EVR_SSC [1:0]. If EVR-SOFTSW is set to 1 and EVR_ZCD is set to 1, the D/A converter, after the lapse of the time defined by EVR_SSC[1:0], repeats the cycle of waiting for the next zero cross point and changing the gain by 1 increment, until the predetermined volume value is reached.
ADRS 10h Bit [7] Name EVR_MUTE Init 1b Description Controls the mute function of the EVR (digital) circuit. 1: Enables MUTE function. 0: Disables MUTE function. [6:0] EVR_GAIN 00h Controls the gain function of the EVR (digital) circuit. 00h: -64dB 57h: +12dB to 2Ch: -9.5dB/0.5dB step 2Bh: -10dB to 0Ch: -41dB/1.0dB step 0Bh: -42dB to 00h: -64dB/2.0dB step 11h [6] EVR_VOLZCD 1b Controls the gain change operation of the EVR (digital) circuit at zerocross timing. 1: Changes the gain at the zerocross timing. 0: Changes the gain without waiting for a zerocross timing. [5:4] EVR_ZCDTM 01b Set the zerocross detection timeout time of the EVR (digital) circuit. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs Valid when [EVR_ZCD] = 1 [2] EVR_SOFTSW 1b Controls the soft switch function of the EVR (digital) circuit. 1: ON 0: OFF [1:0] EVR_VOLTM 00b Set the time of the soft switch function of the EVR (digital) circuit (dos not depend on fs). 11, 10: Inhibited 01: 2.278ms/step, (200ms: When +12dBMUTE) 00: 1.142ms/step, (100ms: When +12dBMUTE)
Digital EVR Circuit Gain Setting Table EVR_GAIN [6:0]
[6:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h GAIN -64dB -62dB -60dB -58dB -56dB -54dB -52dB -50dB -48dB -46dB -44dB -42dB -41dB -40dB -39dB -38dB -37dB -36dB [6:0] 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h GAIN -35dB -34dB -33dB -32dB -31dB -30dB -29dB -28dB -27dB -26dB -25dB -24dB -23dB -22dB -21dB -20dB -19dB -18dB [6:0] 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h GAIN -17dB -16dB -15dB -14dB -13dB -12dB -11dB -10dB -9.5dB -9dB -8.5dB -8dB -7.5dB -7dB -6.5dB -6dB -5.5dB -5dB [6:0] 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h GAIN -4.5dB -4dB -3.5dB -3dB -2.5dB -2dB -1.5dB -1dB -0.5dB +0dB +0.5dB +1dB +1.5dB +2dB +2.5dB +3dB +3.5dB +4dB [6:0] 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h GAIN +4.5dB +5dB +5.5dB +6dB +6.5dB +7dB +7.5dB +8dB +8.5dB +9dB +9.5dB +10dB +10.5dB +11dB +11.5dB +12dB
No.A1345-22/36
LA07410LG
* Playback System Automatic Level Control (ALC) When REC_ALC is set to 0 and PB_ALC is set to 1 (playback system ALC mode), the digital volume control functions as the playback system ALC. Subject the volume value to automatic adjustment so that the digital volume output level is set to the predetermined value. For further details on operation, refer to "Description of ALC/limiter (automatic level control) operation." Noise gate function (NGEN) setting is disabled if playback system ALC mode. When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the digital volume control is set to manual mode, and the gain is fixed to the EVR_GAIN [6:0] register setting. * Line Amplifier The line amplifier provides a gain of 0dB, +4dB, +6dB or +8dB. When LO_MUTE is set to 1, the line output is muted. When LO_PDX is set to 0, the line amplifier is placed in the power down mode. If the line output is set to the high-impedance state when the line amplifier is placed in the power down mode, LO_VREFSW must be set to 0.
ADRS 12h Bit [7] Name LO_MUTE Init 1b Description Controls the mute function of the line out circuit. 1: Enables MUTE function. 0: Disables MUTE function. [6] LO_VREFSW 1b State setting when power of line output id downed* 1: Connects to the reference power source (VREF). 0: Does not connect to the reference power source (VREF). [5:4] LO_GAIN 10b Select the gain of the line out circuit. 11: +8dB 10: +6dB 01: +4dB 00: 0dB * It is not possible to connect between LINE OUT and VREF by setting LO_VREFSW to 1 even if LO_PDX is set to 1.
* Speaker amplifier The speaker amplifier must be started after the selector amplifier output (LOUT2) has been activated and the voltage has stabilized. Either 0dB or +6dB can be selected as the selector amplifier gain using the SEL_GAIN setting. VDDS in the range of 2.7V to 5.5V is supported. (Piezoelectric speaker supported) The amplifier gain is 6dB (+12dB with the BTL output). (With an 8 load) The SPKIN input resistance is 10k (type). When SP_PDX is set to 0, the speaker amplifier is placed in the power down mode. Depending on VDDS, one of the four speaker terminal voltages can be selected using SP_BAIS [1:0] to achieve an optimal dynamic range. * Thermal Shutdown If a chip temperature of 140C or higher is detected while SP_TSD_EN is set 1, the speaker amplifier is placed in the power down mode for protection. The thermal shutdown function is disabled if SP_TSD_EN is set to 0.
ADRS 12h Bit [2] Name SEL_GAIN Init 0b Selector circuit, gain selection 1: +6dB 0: 0dB [1:0] 13h [3:2] SEL_IN SP_IDL 01b 10b Selector input selection setting 00: Prohibition 01: DAC 10: ALC 11: Prohibition Set the idling current of the speaker amplifier circuit 11: 2.0mA 10: 1.0mA 01: 0.67mA 00: 0.5mA [1:0] SP_BIAS 00b Set the bias control of the speaker amplifier circuit 11: 0.833xVDDA 10: 0.766xVDDA 01: 0.666xVDDA 00: 0.5xVDDA 14h [7] SP_OUT_EN 0b Enables or disables the speaker amplifier circuit 1: ON 0: OFF [6] SP_TSD_EN 1b Enables or disables the thermal shutdown function of the speaker amplifier circuit 1: ON 0: OFF See the section on "Speaker Amplifier Start/Stop Sequence" Description
No.A1345-23/36
LA07410LG
* BEEP output A signal input from the BEEP pin or a BEEP sound (pulse wave) generated within the IC can be output from the speaker. (a) EXT-BEEP operation When BPMODE is 01, the signal input to the BEEP pin is output from the speaker. (b) INT-BEEP operation When BPMODE is 10/11, a BEEP signal generated within the IC is output from the speaker.
INTBPST fsig BEEP Output Ton Toff Nrep
Use the BPHZ register to set the pulse frequency, fsig ,the BPTON and BPTOFF registers to set the on/off duty, and the BPCNT register to set the repeat count, Nrep. Then set INTBPST = 01 to output the BEEP sound. Output stops automatically when the specified number of beeps output. When BPMODE is 10 (serial control mode), INTBPST control is carried out according to registers. When BPMODE is 11 (parallel control mode), INTBPST control is carried out using the BEEP pin. Note: When the transition INTBPST = 01 is detected, the BEEP sound starts. When BPMODE is 10 (serial control mode), the BEEP sound is not output even if INTBPST = 1 is sent when INTBPST is set to 1. If toff is 0, the continuous BEEP sound is output during the period given by ton*Nrep. If Nrep is set to infinite, the ton/toff cycle repeats infinitely and stops when INTBPST is set to 0. Output stops when INTBPST is set to 0, even in the middle of BEEP output. The gain from the start of BEEP input until BTL output can be varied within the range -15dB to -21dB, based on the SP_BPVOL[1:0] setting. It is also possible to adjust the sound volume using an external resistor and by setting of 0dB. [Againof approximately -21dB (typ) results with an external 100k connection.]
ADRS 13h Bit [7:6] Name BPMODE Init 00b BEEP output mode setting 11: INT-BEEP operation/parallel control mode 10: INT-BEEP operation/serial control mode 01: EXT-BEEP operation 00: OFF [5:4] BPVOL 11b BEEP gain selection 11: -21dB 10: -18dB 01: -15dB 00: 0dB 2Fh [7:5] [4:0] 30h [7] [6:4] [3:0] BPTON BPTOFF INTBPST BPHZ BPCNT 010b 00110b 0b 011b 0110b INT-BEEP on duty (ton) setting INT-BEEP off duty (toff) setting INT-BEEP starting control (At BPMODE = 10, Valid) INT-BEEP frequency (fsig) setting INT-BEEP number of cycles (Nrep) setting Description
No.A1345-24/36
LA07410LG
BPHZ[2:0] 000 001 010 011 100 101 110 111 fsig 1kHz 2kHz 3kHz 4kHz 5kHz 6kHz 7kHz 8kHz BPTON[2:0] 000 001 010 011 100 101 110 111 Ton 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms BPTOFF[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 BPCNT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Nrep infinite 1 2 3 4 5 6 7 BPCNT[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Nrep 8 9 10 11 12 13 14 15 Toff 0ms 10ms 30ms 50ms 70ms 90ms 110ms 130ms 150ms 170ms 190ms BPTOFF[4:0] 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Toff 210ms 230ms 250ms 270ms 290ms 310ms 330ms 350ms 370ms 390ms
* PLL (a) PLL mode (PLL_PDX = 1) In this mode, the 256fs clock (MCLK) used by the CODEC block is generated from the clock (12, 13.5, 24 and 27MHz frequencies supported) which is input from MCLKIN, and BCLK and LRCK are output. Sampling frequencies (fs) of 7.86kHz to 48kHz are supported. fs setting fs is set by setting the division ratio for each of the three frequency dividers (DIV1, DIV2, and DIV3) in respective registers. 1. Set FCKI[2:0] for the MCLKIN frequency, results in 12MHz or 13.5MHz as the frequency input to DIV1. 2. Set DIV1, DIV2, and DIV3, while referring to the division ratio setting example table.
f MCKOUT =
f MCLKIN x DIV2 = 256fs FCKI x DIV1x DIV3
ex. "FCKI = 2, DIV1 = 125, DIV2 = 128, DIV3 = 2" in case of "MCLKIN = 24MHz, fs = 24kHz" (b) EXT mode (PLL_PDX = 0) In this mode, the 256fs clock (MCLK) from MCLKIN is input and used. When ADF_MASTER is 1, BCLK and LRCK whose frequency is obtained by dividing the frequency of MCLKIN are output. When ADF_MASTER is 0, BLCK and LRCK are external inputs. * In the CODEC block, BCLK and LRCK must be synchronized with MCLK. In PLL mode (PLL_PDX = 1), operation must be performed in BCLK output mode (ADF_MASTER = 1). In EXT mode (PLL_PDX = 0) and when ADF_MASTER is 0, BCLK and LRCK synchronized with MCLK must be input.
No.A1345-25/36
LA07410LG
PLL Block Diagram
SEl_MCLKO H PLL_FCK1[2:0] MCLKIN 24MHz 12MHz or 13.5MHz 27MHz 1/4 1/2 1/2 PLL_DIV1 DIV1 PLL DIV2 PLL_DIV2 DIV3 MCKOUT PLL_PDX EXT PLL 1/8 (32fs) FBCLK 1/4 (64fs) ADF_MASTER 1/256 CODEC L
LRCK BCLK
ADRS 0Dh
Bit [2]
Name FBCLK
Init 0b Sets the BCLK frequency 0: 64fs 1: 32fs
Description
0Eh
[4]
ADF_MASTER
0b
Sets the BCLK, LRCK master/slave 0: slave 1: master
16h
[5:4]
SEL_MCLKO
00b
MCLKO output selection 00: "L" 10: "H" 01/11: MCLKIN[PLL_PDX = 0] or PLL output [PLL_PDX = 1]
16h 17h 18h 19h 1Ah
[0] [7:0] [0] [7:0] [1:0]
PLL_DIV1
07Dh
Sets the basis clock frequency ratio (DIV1) 000h: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 07Dh(125)
PLL_DIV2
080h
Sets the VCO output frequency ratio (DIV2) 000h: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 080h(128)
PLL_DIV3
00b
Sets the MCLK output frequency ratio (DIV3) 00: 1/1 01: 1/2 10: 1/4 11: 1/4
[5:4]
PLL_FCKI
00b
Sets the MCLKIN input frequency ratio 00: 1/1 01: 1/2 10: 1/4 11: 1/4
Frequency Ratio Setting Example Target frequency fs(kHz) 48 44.1 32 24 22.05 16 12 11.025 8 256fs(MHz) 12.288 11.29 8.192 6.144 5.6448 4.096 3.072 2.8224 2.048 DIV1 125 304 271 125 304 271 125 304 271
DIV1 input = 12MHz Frequency Ratio Value DIV2 128 286 185 128 286 185 128 286 185 DIV3 1 1 1 2 2 2 4 4 4 DIV1 245 171 206 245 171 206 245 171 206
DIV1 input = 13.5MHz Frequency Ratio Value DIV2 223 143 125 223 143 125 223 143 125 DIV3 1 1 1 2 2 2 4 4 4
No.A1345-26/36
LA07410LG
* Video Driver
VDREF
REG VREF2 VREF1 VD_DCTL
VDIN
0dB ATT
75
0.1V LPF -6/0dB VD_GAIN 12dB VDOUT
VDIN Sync DC: State of -12.5mV to 162.5mV (At 12.5mV/step, +12dB), -25mV to 325mV (25mV/step, At +6dB) is adjustable to VDOUT Sync DC (100mV). Either 6dB or 12dB can be selected as the total gain of the video amplifier using the internal register setting (VD_GAIN). When the input sync level is within the -12.5mV to 162.5mV (At +12dB)/-25mV to 325mV (At 6dB) range, the output sync level can be adjusted to 100mV using the internal register settings (VD_DCTL [3 : 0]).
ADRS 14h Bit [4] Name VD_GAIN Init 0b Selects the driver gain of the video circuit 0: +6dB 1: +12dB [3:0] VD_DCTL 0001b Selects the input sync level DC OFFSET of the video circuit 0000: -25mV to 1110: 325mV (+6dB) 0000: -12.5mV to 1110: 162.5mV (+12dB) Description
Video Driver Sync DC Level Adjustment Table
VD_DCTL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Input_Sync_DC At +6dB -25mV 0mV 25mV 50mV 75mV 100mV 125mV 150mV 175mV 200mV 225mV 250mV 275mV 300mV 325mV 0mV Input_Sync_DC At +12dB -12.5mV 0mV 12.5mV 25mV 37.5mV 50mV 62.5mV 75mV 87.5mV 100mV 112.5mV 125mV 137.5mV 150mV 162.5mV 0mV Output_Sync_DC 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV 100mV
No.A1345-27/36
LA07410LG
Register Table ADRS (Address): displayed in hexadecimal notation, Init (initial value): displayed in hexadecimal notation Register bits indicated by "0" must be set to 0. Registers indicated with a gray background are for IC testing and their initial values are fixed. All registers (addresses: 00 to 25h) must be loaded with write data (including test registers).
Functions PM1 PM2 MIC ALC1 ALC2 ALC3 ALC4 ALC5 ALC6 ALC7 ALC8 ALC9 ALC10 CODEC1 CODEC2 CODEC3 EVR1 EVR2 LINE/SEL SPK1 SPK2/VIDEO FS PLL1_1 PLL1_2 PLL2_1 PLL2_2 PLL3 FILTER1_A1 FILTER1_A1 FILTER1_A2 FILTER1_A2 FILTER1_B0 FILTER1_B0 FILTER1_B1 FILTER1_B1 FILTER1_B2 FILTER1_B2 FILTER2_A1 FILTER2_A1 FILTER1_A2 FILTER1_A2 ADRS [7:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h Register Data D[7:0] Init 7 00h 00h 10h 12h 24h 34h 34h 04h 56h 49h 0Ah 0Eh 0Eh 02h 00h 00h 80h 54h E1h 38h 41h 08h 00h 7Dh 00h 80h 00h 00h 00h 00h 00h 40h 00h 00h 00h 00h 00h 00h 00h 00h 00h MIC_PDX SYNC_CLR 0 0 0 0 0 0 ALC_FULLEN ALC_NGEN 0 0 0 FILTER2 0 0 EVR_MUTE 0 LO_MUTE BPMODE[1] SP_OUT_EN 0 0 PLL_DIV1[7] 0 PLL_DIV2[7] 0 A1[15] A1[7] A2[15] A2[7] B0[15] B0[7] B1[15] B1[7] B2[15] B2[7] A1[15] A1[7] A2[15] A2[7] 6 MIC_PWR_PDX 0 0 ALC_VAL[2] ALC_THA[2] ALC_THR1[2] ALC_THR2[2] 0 ALC_ZCD ALC_NGTH[2] 0 0 0 FILTER1 0 0 EVR_GAIN[6] EVR_VOLZCD LO_VREFSW BPMODE[0] SP_TSD_EN 0 0 PLL_DIV1[6] 0 PLL_DIV2[6] 0 A1[14] A1[6] A2[14] A2[6] B0[14] B0[6] B1[14] B1[6] B2[14] B2[6] A1[14] A1[6] A2[14] A2[6] 5 PGA_PDX VREF_BIAS[1] MIC_GAIN[1] ALC_VAL[1] ALC_THA[1] ALC_THR1[1] ALC_THR2[1] 0 4 ADC_PDX VREF_BIAS[0] MIC_GAIN[0] ALC_VAL[0] ALC_THA[0] ALC_THR1[0] ALC_THR2[0] 0 3 DAC_PDX 0 0 0 0 0 0 0 ALC_TLIM[1] ALC_NGDT[1] 1 ALC_VMAX[3] ALC_GAIN[3] AD_MUTE ADF_DAC_INV 0 EVR_GAIN[3] 0 0 SP_IDL[1] VD_DCTL[3] FS[3] 0 PLL_DIV1[3] 0 PLL_DIV2[3] 0 A1[11] A1[3] A2[11] A2[3] B0[11] B0[3] B1[11] B1[3] B2[11] B2[3] A1[11] A1[3] A2[11] A2[3] 2 SEL_PDX PLL_PDX 0 ALC_FA1[2] ALC_FA2[2] ALC_FR1[2] ALC_FR2[2] ALC_FR3[2] ALC_TLIM[0] ALC_NGDT[0] 0 ALC_VMAX[2] ALC_GAIN[2] FBCLK ADF_ADC_INV 0 EVR_GAIN[2] EVR_SOFTSW SEL_GAIN SP_IDL[0] VD_DCTL[2] FS[2] 0 PLL_DIV1[2] 0 PLL_DIV2[2] 0 A1[10] A1[2] A2[10] A2[2] B0[10] B0[2] B1[10] B1[2] B2[10] B2[2] A1[10] A1[2] A2[10] A2[2] 1 LO_PDX REG_PDX 0 ALC_FA1[1] ALC_FA2[1] ALC_FR1[1] ALC_FR2[1] ALC_FR3[1] ALC_RWT[1] ALC_NGRT[1] 1 ALC_VMAX[1] ALC_GAIN[1] REC_ALC ADF_MODE[1] SEL_USE_DSP EVR_GAIN[1] 0 SP_PDX VD_PDX 0 ALC_FA1[0] ALC_FA2[0] ALC_FR1[0] ALC_FR2[0] ALC_FR3[0] ALC_RWT[0] ALC_NGRT[0] 0 ALC_VMAX[0] ALC_GAIN[0] PB_ALC ADF_MODE[0] 0 EVR_GAIN[0]
ALC_ZCDTM[1] ALC_ZCDTM[0] ALC_NGTH[1] 0 ALC_VMAX[5] ALC_GAIN[5] WIND_CUT[1] 0 ADF_LB EVR_GAIN[5] ALC_NGTH[0] 0 ALC_VMAX[4] ALC_GAIN[4] WIND_CUT[0] ADF_MASTER 0 EVR_GAIN[4]
EVR_ZCDTM[1] EVR_ZCDTM[0] LO_GAIN[1] BPVOL[1] 0 0 LO_GAIN[0] BPVOL[0] VD_GAIN 0
EVR_VOLTM[1] EVR_VOLTM[0] SEL_IN[1] SP_BIAS[1] VD_DCTL[1] FS[1] 0 PLL_DIV1[1] 0 PLL_DIV2[1] PLL_DIV3[1] A1[9] A1[1] A2[9] A2[1] B0[9] B0[1] B1[9] B1[1] B2[9] B2[1] A1[9] A1[1] A2[9] A2[1] SEL_IN[0] SP_BIAS[0] VD_DCTL[0] FS[0] PLL_DIV1[8] PLL_DIV1[0] PLL_DIV2[8] PLL_DIV2[0] PLL_DIV3[0] A1[8] A1[0] A2[8] A2[0] B0[8] B0[0] B1[8] B1[0] B2[8] B2[0] A1[8] A1[0] A2[8] A2[0]
SEL_MCLKO[1] SEL_MCLKO[0] PLL_DIV1[5] 0 PLL_DIV2[5] PLL_FCKI[1] A1[13] A1[5] A2[13] A2[5] B0[13] B0[5] B1[13] B1[5] B2[13] B2[5] A1[13] A1[5] A2[13] A2[5] PLL_DIV1[4] 0 PLL_DIV2[4] PLL_FCKI[0] A1[12] A1[4] A2[12] A2[4] B0[12] B0[4] B1[12] B1[4] B2[12] B2[4] A1[12] A1[4] A2[12] A2[4]
Continued on next page
No.A1345-28/36
LA07410LG
Continued from precceding page.
Functions FILTER1_B0 FILTER1_B0 FILTER1_B1 FILTER1_B1 FILTER1_B2 FILTER1_B2 SPK_BEEP1 SPK_BEEP2 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 ADRS [7:0] 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h Register Data D[7:0] Init 7 40h 00h 00h 00h 00h 00h 46h 36h 00h 00h 00h 9Dh 10h A3h 01h 21h 00h B0[15] B0[7] B1[15] B1[7] B2[15] B2[7] BPTON[2] INTBPST 0 0 0 1 0 1 0 0 0 6 B0[14] B0[6] B1[14] B1[6] B2[14] B2[6] BPTON[1] BPHZ[2] 0 0 0 0 0 0 0 0 0 5 B0[13] B0[5] B1[13] B1[5] B2[13] B2[5] BPTON[0] BPHZ[1] 0 0 0 0 0 1 0 1 0 4 B0[12] B0[4] B1[12] B1[4] B2[12] B2[4] BPTOFF[4] BPHZ[0] 0 0 0 1 1 0 0 0 0 3 B0[11] B0[3] B1[11] B1[3] B2[11] B2[3] BPTOFF[3] BPCNT[3] 0 0 0 1 0 0 0 0 0 2 B0[10] B0[2] B1[10] B1[2] B2[10] B2[2] BPTOFF[2] BPCNT[2] 0 0 0 1 0 0 0 0 0 1 B0[9] B0[1] B1[9] B1[1] B2[9] B2[1] BPTOFF[1] BPCNT[1] 0 0 0 0 0 1 0 0 0 0 B0[8] B0[0] B1[8] B1[0] B2[8] B2[0] BPTOFF[0] BPCNT[0] 0 0 0 1 0 1 1 1 0
Register Description
ADRS 00h Bit [7] [6] [5] [4] [3] [2] [1] [0] 01h [7] [5] [4] [2] [1] [0] 02h 03h [5:4] [6:4] PLL_PDX REG_PDX VD_PDX MIC_GAIN ALC_VAL 0b 0b 0b 01b 001b Name MIC_PDX MIC_PWR_PDX PGA_PDX ADC_PDX DAC_PDX SEL_PDX LO_PDX SP_PDX SYNC_CLR VREF_BIAS Init 0b 0b 0b 0b 0b 0b 0b 0b 0b 00b MIC amplifier circuit, power control MIC Power circuit, power control PGA circuit, power control ADC circuit, power control DAC circuit, power control Selector circuit, power control Line out circuit circuit, power control Speaker amplifier circuit, power control Internal logic clear Description 1: power on 1: power on 1: power on 1: power on 1: power on 1: power on 1: power on 1: power on 0: power down 0: power down 0: power down 0: power down 0: power down 0: power down 0: power down 0: power down
1: ON 0: OFF(normal operation)
Reference voltage circuit (VREF pin) setting 00: Power down 11: Normal operation 10: Quick rise to reference voltage 01: IREF ON/VREF OFF PLL circuit, power control REG circuit, power control Video driver circuit, power control MIC amplifier circuit, gain setting Set the ALC limiter level 000: -3dBFS 001: -4dBFS 010: -5dBFS 011: -6dBFS 100: -7dBFS 101: -8dBFS 110: -9dBFS 111: -10dBFS 1: power on 1: power on 1: power on 0: power down 0: power down 0: power down
11: +26dB 10: +20dB 01: 0dB 00: 0dB
[2:0] 04h [6:4] [2:0] 05h [6:4] [2:0] 06h [6:4] [2:0] 07h [2:0]
ALC_FA1 ALC_THA ALC_FA2 ALC_THR1 ALC_FR1 ALC_THR2 ALC_FR2 ALC_FR3
010b 010b 100b 011b 100b 011b 100b 100b
Attack coefficient 1 setting Set the attack speed switch over thresh Attack coefficient 2 setting Set the recovery speed switch over thresh 1 Recovery coefficient 1 setting Set the recovery speed switch over thresh 2 Recovery coefficient 2 setting Recovery coefficient 3 setting
Continued on next page
No.A1345-29/36
LA07410LG
Continued from precceding page
ADRS 08h Bit [7] [6] [5:4] [3:2] [1:0] 09h [7] [6:4] [3:2] [1:0] 0Bh 0Ch 0Dh [5:0] [5:0] [7] [6] [5:4] [3] [2] [1:0] 0Eh [4] [3] [2] [1:0] 0Fh [5] [1] 10h [7] Name ALC_FULLEN ALC_ZCD ALC_ZCDTM ALC_TLIM ALC_RWT ALC_NGEN ALC_NGTH ALC_NGDT ALC_NGRT ALC_VMAX ALC_GAIN FILTER2 FILTER1 WIND_CUT AD_MUTE FBCLK REC_ALC PB_ALC ADF_MASTER ADF_DAC_INV ADF_ADC_INV ADF_MODE ADF_LB SEL_USE_DSP EVR_MUTE 0b 0b 0b 00b 0b 0b 1b ADF circuit 1: Master mode 0: Slave mode ADF circuit, DAC input data setting 1: Inverted 0: Non-inverted ADF circuit, ADC input data setting 1: Inverted 0: Non-inverted ADF circuit, Format setting 11, 10: right-justified 01: left-justified 00: I2S Loopback setting 1: Internal loopback is done 0: Internal loopback is not done DSP route setting 1: PB (DAC) side 0: REC(ADC) side Controls the mute function of the EVR (digital) circuit. 1: Enables MUTE function. 0: Disables MUTE function. [6:0] EVR_GAIN 00h Controls the gain function of the EVR (digital) circuit. 00h: -64dB 57h: +12dB to 2Ch: -9.5dB /0.5dB step 2Bh: -10dB to 0Ch: -41dB /1.0dB step 0Bh: -42dB to 00h: -64dB /2.0dB step 11h [6] [5:4] EVR_VOLZCD EVR_ZCDTM 1b 01b Controls the gain change operation of the EVR (digital) circuit at zerocross timing. 1: ON 0: OFF Set the zerocross detection timeout time of the EVR (digital) circuit. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs Valid when [EVR_ZCD] = 1 [2] [1:0] EVR_SOFTSW EVR_VOLTM 1b 00b Controls the soft switch function of the EVR (digital) circuit. 1: ON 0: OFF Set the time of the soft switch function of the EVR (digital) circuit (dos not depend on fs). 01: 2.278ms/step, (200ms: When +12dBMUTE) 00: 1.142ms/step, (100ms: When +12dBMUTE) 11, 10: Set prohibition 12h [7] [6] LO_MUTE LO_VREFSW 1b 1b Line out circuit, MUTE function 1: Enables MUTE function 0: Disables MUTE function State setting when power of lineout is downed 1: Connects to the reference power source (VREF) 0: Does not connects to the reference power source (VREF) [5:4] [2] [1:0] 13h [7:6] [5:4] [3:2] [1:0] LO_GAIN SEL_GAIN SEL_IN BPMODE BPVOL SP_IDL SP_BIAS 10b 0b 01b 00b 11b 10b 00b Line out circuit, gain selection 11: +8dB 10: +6dB 01: +4dB 00: 0dB Selector circuit, gain selection 1: +6dB 0: 0dB Selector input selection setting 00: Prohibition 01: DAC 10: ALC 11: Prohibition Init 0b 1b 01b 01b 10b 0b 100b 10b 01b 0Eh 0Eh 0b 0b 00b 0b 0b 10b Full scale detection mode setting. Controls the gain change operation at zerocross timing. Description 1: ON 0: OFF 1: ON 0: OFF
Set the zerocross detection timeout time. Valid when [ALC_ZCD] = 1. 11: 8192/fs 10: 4096/fs 01: 2048/fs 00: 1024/fs Set the inter-zerocross attack limit. 11: 4dB 10: 2dB 01: 1dB 00: 0.5dB Valid when [ALC_ZCD] = 1 Set the recovery alert time 11: 1024/fs 10: 512/fs 01: 256/fs 00: 128/fs Set the noise gate function 1: Valid 0: Invalid Set the noise gate silent detection thresh level Set the noise gate silent detection time/Set the gain attenuation time Set the noise gate reset time Set the maximum PGA gain value (Init value 0Eh: 0dB) Set the manual mode PGA gain value (Init value 0Eh: 0dB) Programmable Filter2 setting 1: ON 0: OFF Programmable Filter1 setting 1: ON 0: OFF WIND_CUT function (HPF fc setting) 11: 400Hz 10: 300Hz 01: 200Hz 00: OFF ADC output MUTE setting 1: Enables MUTE function 0: Disables MUTE Set the BCLK frequency 1: 32fs 0: 64fs Set the ALC mode 10: REC ALC 01: PB ALC 00/11: ALC OFF
BEEP output mode setting 01: EXT-BEEP operation 00: OFF 11: INT-BEEP operation/parallel control 10: INT-BEEP operation/serial control BEEP gain selection 11: -21dB 10: -18dB 01: -15dB 00: 0dB Set the idling current of the speaker amplifier circuit 11: 2.0mA 10: 1.0mA 01: 0.67mA 00: 0.5mA Set the bias control of the speaker amplifier circuit 11: 0.833xVDDA 10: 0.766xVDDA 01: 0.666xVDDA 00: 0.5xVDDA
Continued on next page No.A1345-30/36
LA07410LG
Continued from preceding page
ADRS 14h Bit [7] Name SP_OUT_EN Init 0b 1: ON 0: OFF [6] SP_TSD_EN 1b Enables or disables the thermal shutdown function of the speaker amplifier circuit 1: ON 0: OFF [4] [3:0] VD_GAIN VD_DCTL 0b 0001b Selects the driver gain of video circuit 0: +6dB 1: +12dB Select the Input Sync Level DC OFFSET of video circuit 0000: -25mV to 1110: 325mV (+6dB) 0000: -12.5mV to 1110: 162.5mV (+12dB) 15h [3:0] FS 1000b Sampling frequency setting 1000: 48kHz / 0111: 44.1kHz / 0110: 32kHz / 0101: 24kHz 0100: 22.05kHz / 0011: 16kHz / 0010: 12kHz / 0001: 11.025kHz/ 0000: 8kHz 16h [5:4] SEL_MCLKO 00b MCLKO output selection 00: "L" 00: "H" Description Enables or disables the speaker amplifier circuit
01/11: MCLKIN [PLL_PDX = 0] or PLL output [PLL_PDX = 1] 16h 17h 18h 19h 1Ah [0] [7:0] [0] [7:0] [5:4] [1:0] 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:5] [4:0] 30h [7] [6:4] [3:0] 31h to 39h MIC = Microphone amp ALC = Automatic Level Control ADC = AD Converter DAC = DA Converter EVR = Electronic Variable Resistor ADF = Audio Data Format PGA = Programmable Gain Amplifier ADRS = Address Init = Initial value Nh = N denotes a hexadecimal number Nb = N denotes a binary number PLL_FCKI PLL_DIV3 A1[15:8] A1[7:0] A2[15:8] A2[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0] A1[15:8] A1[7:0] A2[15:8] A2[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B2[15:8] B2[7:0] BPTON BPTOFF INTBPST BPHZ BPCNT TEST 00b 00b 00h 00h 00h 00h 40h 00h 00h 00h 00h 00h 00h 00h 00h 00h 40h 00h 00h 00h 00h 00h 010b 00110 b 0b 011b 0110b INT-BEEP starting control (At BPMODE = 10 valid) INT-BEEP frequency (fsig) setting INT-BEEP number of cycles (Nrep) setting INT-BEEP on duty(ton) setting INT-BEEP off duty(toff) setting Sets the programmable Filter2 coefficient b2 Sets the programmable Filter2 coefficient b1 Sets the programmable Filter2 coefficient b0 Sets the programmable Filter2 coefficient a2 Sets the programmable Filter2 coefficient a1 Sets the programmable Filter1 coefficient b2 Sets the programmable Filter1 coefficient b1 Sets the programmable Filter1 coefficient b0 Sets the programmable Filter1 coefficient a2 PLL_DIV2 080h PLL_DIV1 07Dh Sets the basis clock frequency ratio (DIV1) 000H: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 07Dh(125) Sets the VCO output frequency ratio (DIV2) 000H: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 080h(128) Sets the MCLKIN input frequency ratio 00: 1/1 01: 1/2 10: 1/4 11: 1/4 Sets the MCLK output frequency ratio (DIV3) 00: 1/1 01: 1/2 10: 1/4 11: 1/4 Sets the programmable Filter1 coefficient a1
No.A1345-31/36
LA07410LG
Control Sequence
Reference voltage, line out start/stop sequence
Common refernce voltage VREF_BIAS[1]
VREF_BIAS[0]
VREF pin
0.5xVDDA
Line output circuit Line output signal LO_PDX t3 LO_MUTE 0.5xVDDA LOUT1 pin t0 t1 t2 t5 t3
t4
* Recommendation value t0 > 1ms (Pull down period, at already when LOUT1 pin is GND level.) t1 > 100ms (Rapid charge period, at VREF pin connected capacity is 4.7F) t2 > 300ms (LOUT1 charge time) t3 > 1ms (Waiting time of MUTE ON/OFF) t4 > 0s t5 > 300ms (Pull down period) * It makes it to LO_VREFSW = 1 usually. * LO_VREFSW function at power down (LO_PDX = 0) LO_VREFSW = 1: LOUT1 pin becomes VREF level output LO_VREFSW = 0: LOUT1 pin becomes Hi-Z
Speaker Amplifier Start/Stop Sequence
Speaker amplifier input signal
SP_PDX t4 SP_OUT_EN t1 t2 t3 t2 t3 0.5xVDDS
SPOUTP/N pin (Speaker output)
* Recommendation value t1 > 5ms (Speaker bias start-up time) t2 10ms (Processing period when POP sound is decreased. Input signal recommends MUTE.) t3 > 15ms t4 > 1ms * External capacitance connected to SPKIN pin is 0.1F * SP_OUT_EN must be set to 0 when power down (SP_PDX = 0) mode.
No.A1345-32/36
LA07410LG
Digital Filter
ADC/DAC digital filters
ADC Digtal Filter Frequency Response
0 0.15 - 20 0.1
0.2
ADC Digtal Filter Frequency Response (passband)
Amplitude - dB
- 40 - 60 - 80 - 100 - 120 - 140 0 1 2 3 4
Amplitude - dB
0.05 0 - 0.05 - 0.1 - 0.15 - 0.2 0 0.1 0.2 0.3 0.4 0.5
Frequency - Xfs
0
Frequency - Xfs
0.05 0.04
DAC FIR Filter Frequency Response
DAC FIR Filter Ripple
- 20 0.03 - 40 0.02
Gain - dB
Gain - dB
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
- 60
0.01 0 - 0.01 - 0.02 - 0.03
- 80
- 100
- 120 - 0.04 - 140 - 0.05 0 0.1 0.2 0.3 0.4 0.5
Frequency - fs
Frequency - fs
No.A1345-33/36
LA07410LG
Programmable digital filter setting example
Notch Filter
1kHz 2kHz fb = 4kHz 1kHz 2kHz fb = 4kHz
@fs = 48kHz
High Shelf Filter
Q = 0.7 f0 = 20kHz gain (-6dB)
5 0 -5 - 10
5
0
Response - dB
- 15 - 20 - 25 - 30 - 35 - 40 - 45 0 5 10 15 20 25
Response - dB
-5
- 10
f0 = 15kHz
- 15
(-12dB)
f0 = 16kHz f0 = 8kHz
- 20
(-20dB)
0 5 10 15 20 25
- 25
f - kHz
15
f - kHz
15
Equalizer
f0 = 14kHz
Equalizer
f0 = 8kHz
10
10
fb = 8kHz
gain +12dB gain +6dB
fb = 4kHz
gain +12dB gain +6dB
Response - dB
fb = 2kHz
0
Response - dB
5
5
fb = 1kHz
0
-5
- 10
fb = 1kHz gain -6dB fb = 4kHz gain -12dB f0 = 5kHz
gain -6dB
-5
fb = 3kHz fb = 12kHz
gain -12dB
- 10
f0 = 16kHz
- 15 10 15 20 25 0 5 10 15 20 25
- 15 0 5
f - kHz
0
f - kHz Q = 0.7
5 0
LPF
f0 = 16 Hz
HPF
8k
- 20
-5 - 10
Response - dB
Response - dB
- 40 - 60 - 80 - 100 - 120 - 140 0.1 2 3 57 1 2 3
- 15 - 20 - 25 - 30 - 35 - 40 - 45
z 0H z = 0H f0 20 z 0H 40 z H 1k 10
4k
f - kHz
Hz
2k
kHz
5 7 10
Hz
2
3
5 7 100
0.01
2
3
5 7 0.1
2
3
57
1
2
3
5 7 10
f - kHz
No.A1345-34/36
LA07410LG
Checkpoints
The user is responsible for ascertaining whether this IC can be adopted for the set to be mass production by the user, including the various condition for mounting in the set. 1) Power supply * The 3.0V type and 3.0V/5.0V type are available as the power supply pins. 1.8V type: Digital power supply I/O (VDDIO) 3.0V type: Digital power supply (VDD), analog power supplies (VDDR, VDDA, VDDV, VDDP) 3.0V/5.0V type: Analog power supply (VDDS) * The power-on sequence is such that the power is first applied in sequence starting with the circuits that operate using a high voltage and the power is turned off in sequence starting with the circuits that operate using a low voltage. 2) Resetting * At power-on, the PDNB pin must be set to low without fail. (A) or (B) is executed as shown in the figure below.
95% power startup level Power pin tD PDNB (A) tD PDNB Normal operation start
0.8V
0.8V tD > 1s (B)
Notes: (A) is reset at the same time as the power is first applied. (B) is reset immediately after the power is first applied. The MCLKIN pin clock input must be provided without fail during either the (A) or (B) period.
3) 3-line serial setting * Whenever 3-line serial setting is to be performed, it must be done where the MCLKIN input has stabilized without fail. * If garbled data is found, restart the IC (switching the state of the PDNB pin from low to high) and perform 3-line serial setting again.
No.A1345-35/36
LA07410LG
Application Circuit Example
3.0V
VDDR
1F
10F 3900pF
0.068F
ALCIN
MICOUT
VCOFIL
VDDP
3.3k
VREG
10F
1F
MCLKIN
MCLKO
VSSR
VDDR
0.1F MICPWR 2.2k to 4.7k 0.47F MICINP 0.47F MICINN VDDA 10F VSSA
BCLK
LRCK ADOUT DAIN
VDDIO
VDDIO 10F DVDD DVSS
DVDD
10F
VREF 4.7F
P/ DSP
LINE OUT
LOUT1 0.1F LOUT2 0.1F SPKIN 0.01F
TESTIN
SDA
SCK
SPOUTN
BEEP
CSB
SPOUTP
VDOUT
VDREF
VDDV
VSSV
VDDS
10F
75
10F
VDDS
VDDV Video out
1F
PDNB
VSSS
VDIN
VIDEO DAC
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice. PS No.A1345-36/36

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